Wafer Specifications

Useful information related to Crystallographic Properties of Silicon, industry standards, doping and resistivity, and more.

Doping and Resistivity

A p-type wafer is usually doped with Boron, although Gallium can also be used (rare). P+ wafers are heavily doped and typically have resistances of <1 Ohm/cm2. P+ wafers are often used for Epi substrates. P- wafers are lightly doped with typical resistances of >1 Ohm/cm2. The most common crystal orientations for P-type wafers are {100} and {111}.

N-type wafers are doped with Phosphorus, Antimony, or Arsenic. N+ wafers are heavily doped with resistances <1 Ohm/cm2. N- wafers are lightly doped with resistances >1 Ohm/cm2. Resistivity is very important to good electronic devices and for growing uniform thermal oxides. High resistivity silicon can only be produced using the Float Zone (FZ) crystal growth method, which does not use a crucible during crystal growth. The Czochralski (CZ) method uses a quartz crucible during crystal growth, and oxygen from the crucible unintentionally dopes the material. The oxygen dopant behaves as an n-type impurity and impedes high resistivity. Low resistivity n-type material is achieved using Arsenic doping.

Wafer flats in relation to doping

Standards by which wafer quality is measured


1. Light point defects (LPDs) - Unwanted particles on surface of wafer.

2. Particles measured by total number found across a certain area of wafer. Some edge exclusions are applied.


1. Total thickness variation (TTV) — Absolute difference in thickness between the thickest and thinnest parts of wafer. A typical value on a 8" wafer would be less than 15 um.

2. Warp - The difference between minimum and maximum values of the wafer surface measured from a reference plane (usually the backside of the wafer). Deviations include both concave and convex variations. Warp is a bulk property. A good warp number on an 8" wafer is less than 20 um.

3. Global Total Indicated Reading (GTIR) — Maximum peak to valley deviation of a wafer from a given reference plane (often the backside of the wafer).

4. Site TIR - similar to GTIR except on smaller sites on wafer. Site TIR can be a parameter of greater importance then global TIR when resolving submicron geometries. Bow - Concavity or deformation of the wafer measured from the center independent of any thickness variation. Bow is a bulk property. Good bow on a 8" prime wafer is less than 30 um.


1. Defects in Silicon are one of the principle causes for rejection of Silicon wafers.

2. There are many defects associated with Silicon wafers. Most are caught at the Silicon Manufacturer, but some are not. Some so called "Prime wafers" not purchased from manufacturers may be rejects.

3. Wafer defects range from pits and micro-scratches in the Silicon surface to imperfections buried in the Silicon bulk. Crystalline defects which are introduced into the crystals during the crystal growth are point defects, dislocations, stacking faults, twins, inclusions, precipitates, and microdefects.

4. Point defects - include vacancies, interstitials, antisite defects, foreign atoms. Melt stoichiometry controls the concentration of point defects (and electrical properties of material).

5. Dislocations - Originate during bulk crystal growth from three mechanisms:

  • Nonuniform heat flow during solidification resulting in thermal stress.
  • Condensation of excess point defects forming dislocation loops.
  • Propagation of dislocations from defective seed crystal or punching out of dislocations from foreign particles or inclusions.

Parameters affecting dislocation density:

  • Seed quality and necking
  • Cone angle
  • Ambient pressure
  • Melt stoichiometry
  • Crystal diameter

6. Stacking faults and twins - two dimensional defects observed frequently in III-V semiconductor crystals. A stacking flaw is a flaw in the stacking sequence of atomic planes in the crystal lattice. A twin represents two regions in the crystal with one region a mirror reflection of the other across a lattice plane (twin plane) that is common to both regions. Twinning can occur as a result from:

  • Nucleation at the crucible wall
  • Deviation from melt stoichiometry
  • Excessive thermal stresses due to variations in crystal diameter
  • Instabilities in the shape of the crystal growth front
  • Thermal decomposition following growth
  • Excessive facet formation

7. Line defects - also known as 'dislocations', which can be classified as one of the following:

  • Edge dislocation (see above).
  • Screw dislocation (see above).
  • Mixed dislocation, which contains both edge and screw dislocation components. 

8. Plane defects - also known as 'area' defects, which can be classified as one of the following:

  • Stacking faults (see above).
  • Grain boundaries - the transition or interface between crystals whose atomic arrangements are different in orientation with respect to each other.
  • Twin boundaries (see above).

9. Volume defects - also known as 'bulk' defects, which include:

  • Voids.
  • Precipitates of extrinsic and intrinsic point defects.


Prime wafers - "Prime" refers to the highest possible grade of a silicon wafer, however there are a variety of "prime" wafers. SEMI indicates the bulk, surface, and physical properties required to label silicon wafers as true "Prime Wafers," however wafers meeting these specs are rare and quite expensive. A true prime wafer is a device quality wafer that any major fab could use for the latest technology semiconductor devices. A true prime wafer will be very smooth, site inspected for flatness meeting a spec of at least .3um on a 20mm x 20mm site and defect free.

Test wafers - A silicon wafer used in process monitoring or other testing. Bulk, surface and physical properties are less stringent than required for prime wafers. Test wafers are often wafers failed one or more specifications in the attempt to make prime wafers. Test wafers have no flatness spec, no backside specs, and a very wide resistivity range. Unless a process is highly sensitive to uniformity, test wafers generally perform well.

Reclaim wafers - A wafer that has been used in a semiconductor manufacturing process after which the surface is refinished (repolished) to a test grade quality. As larger diameter silicon wafers were being developed, the cost of these wafers increased. In order to provide savings to customers, the wafer reclaim process was developed. Reclaimed wafers are stripped of films, metals or other contaminants, cleaned and then polished to specification. This allows three and four uses out of one wafer as the waver is thinned with each re-polish. Typically reclaimed wafers are sold without tight restrictions on resistivity.

Recycled wafers - A wafer that has been cleaned to a degree suitable for reprocessing. Only certain surface treatments can be chemically removed without damaging the silicon substrate.

Epi wafers - have a thin layer of N- silicon grown on the surface of a P+ (Boron) wafer providing a very flat surface suitable for submicron lithography. Epi wafers are a less expensive alternative to high priced Prime wafers discussed above. Silicon atoms are deposited on a bare silicon wafer in a CVD reactor. When the chemical reactants are controlled and the system parameters are set correctly, the depositing atoms arrive at the wafer surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the wafer atoms. Thus an epitaxial film deposited on a <111>-oriented wafer will take on a <111> orientation. If a dielectric or other film is already present on the wafer, the epi layer will be polysilicon. Epi wafers will always have a characteristic oxide backseal on them (usually 3-5,000Å). This oxide is placed on the backside of the wafer to prevent Boron from outgassing and contaminating the n-doped front side during the high temperature deposition of the epi-layer.

Furnace Grade - Furnace grade wafers have very tightly controlled electrical characteristics. Typically they are used for high temperature applications or thin film depositions. Furnace grade wafers display very tightly controlled Oxygen content, resistivity, radial resistivity gradient (RRG) and carbon content. The wafers are also doped very evenly. All of these factors help films grow uniformly without slip lines or stress fractures.

Coin-roll wafers - Wafers that fail spec for any reason at all different steps of the Silicon wafer manufacturing process are collected and sold as coin-roll wafers. Thus some of the wafers are unpolished or scratched and they have different resistivities and crystal orientations. Silicon vendors buy these wafers in large containers with hundreds of wafers stacked on top of each other inside, resembling a roll of coins. These wafers are sorted for type and resistivity and recycled into test wafers.

Particle wafers - Particle grade wafers typically refer to 300 mm wafers and have a minimal amount of contaminants, or particles. Particles are measured at various sizes, 0.09 um, 0.12 um, 0.16 um. 0.20 and 0.30 are common specifications. The number of particles at a certain size is limited to a predetermined number, 10, 20, 50, etc. The specification is written: <50@>0.12 um. This means there are less than or equal to 50 particles greater than 0.12 um in size on the entire wafer.

Mechanical grade wafers -- .... Although the specifications can be applied to any diameter wafer, the term "mechanical grade" most often refers to a 300 mm specification.

Backside Treatment

1. Wafers typically etched (acid = smooth quasimirror; caustic = dull finish)

2. Gettering - wafers receive a backside coating of Polysilicon. In subsequent process steps, this backside treatment will draw defects in the Silicon towards the backside of the wafer and away from the front side where the devices are being built.

3. Double polished

SEMI Standards

Wafers conforming to SEMI Standards will have the characteristics listed below:

Diameter of wafer: 50 mm (2")

1. Primary flat on (01 T) plane ± 0.5°.

2. Secondary flat 90° ± 1° ccw to primary flat.

3. Primary flat length: 15.9 ± 1.5 mm.

4. Secondary flat length: 8.0 ± 1.5 mm.

Diameter of wafer: 75 mm (3")

1. Primary flat on (01 T) plane ± 0.5°.

2. Secondary flat 90° ± 1° ccw to primary flat.

3. Primary flat length: 22.2 ± 2.0 mm.

4. Secondary flat length: 11.2 ± 1.5 mm.

Diameter of wafer: 100 mm (4") 

Thickness: 525 um (20.5 mils)
Primary flat length: 32.5 mm
Secondary flat length: 18.0 mm
Bow, max: 40 um
Warp, max: 40 um
TTV (flatness), max: 10 um
Primary flat orientation: <110>

Diameter of wafer: 150 mm (6") 

Thickness: 675 um (26.3 mils)
Primary flat length: 57.5 mm
Secondary flat length: 37.5 mm
Bow, max: 60 um
Warp, max: 60 um
TTV (flatness), max: 10 um
Primary flat orientation: <110>


Using a diamond scribe:

1. Place wafer on a soft surface such as a cleanroom towel.

2. With a diamond scribe, make a small nick in the wafer at the major flat.

3. Apply pressure to the immediate left or right of the nick in order to cleave the wafer. If possible, applying pressure to backside of wafer over nicked site works best.

4. Make another nick in the cleaved piece and repeat as above. Cleaves will run according to the following crystal orientations:

Silicon If the crystal orientation of the Si is <100> the cleaved pieces form rectangles (cleave at 90 deg. angles). Crystallographic Properties of Si

If the crystal orientation of the Si is <111> the cleaved pieces form triangles (cleave at 60 deg. angles). <111> material has triangular crystal structure. You have to scribe up through the base of the triangle, as opposed to the vertex of the triangle, so orientation is important. Usually, this is delineated by a flat along the 110 plane. Cleaving samples on {111} wafers for SEM imaging can be difficult.

GaAs: cleave plane is the <110> plane.